1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices, and more specifically, to an improved dual epitaxial process for semiconductor MOS devices.
2. Description of the Prior Art
As known in the art, metal-oxide-semiconductor field-effect transistors (MOSFETs) have been scaled down through various technology nodes. To enhance carrier mobility and improve device performance, strained source/drain features (e.g., stressor regions) have been introduced. Stress distorts or strains the semiconductor crystal lattice, which affects the band alignment and charge transport properties of the semiconductor.
Typically, compressive strain increases charge carrier mobility in a p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) channel and tensile strain increases charge carrier mobility in an n-type metal-oxide semiconductor field-effect transistor (nMOSFET) channel. Silicon-germanium (SiGe) is a typical epitaxial material utilized to induce compressive strain in pMOS channel for increased hole mobility. Tensile strain may be achieved for increased electron mobility in nMOS channel by the introduction of silicon carbide (SiC) or silicon phosphate (SiP).
However, the prior art dual epitaxial process for semiconductor MOS devices suffers from selective loss defect and SiGe fall-on issue (i.e. SiGe grains grown in nMOS region). It is therefore desirable to have improved methods and structures for utilizing such epitaxial material regions.